1. Technical Field of the Invention
The present invention relates in a general manner to the management of a standby state of a microprocessor. The invention relates more particularly to a microprocessor and to a method of control of such a microprocessor to place it in a standby state during a determined period.
2. Description of Related Art
It is known that in microprocessor systems the data transfer speed may differ from one peripheral to another. Such peripherals are by way of example memories of different architecture whose data transfer rates are different.
Thus, when the processing of an instruction is dependent on the result of a previously processed instruction, and if the instructions call upon information stored in memories of different architecture, data congestion may appear at the microprocessor. For example, the second instruction may need an address computed by the first instruction.
It is therefore necessary to synchronize the transfer of data, hence the processing of the instructions, at the microprocessor which executes operations associated with the instructions.
To avoid this data congestion, one solution is to deliberately slow down the processing of one or more instructions. For example, the solution consists in inserting a standby state of a determined number of clock cycles between the processing of the instructions concerned. The microprocessor is thus in a standby state. Stated otherwise, a standby state is generated so as to tailor transfer times during communications between several peripherals managed by the microprocessor or to sharpen the execution time of a program of any application.
Several procedures are known in prior art for generating a standby state during a determined period corresponding to a determined number of clock cycles.
A first procedure known in the state of the art consists in providing for the implementation, in a program, of an NOP instruction (standing for “No Operation”) belonging to an instruction set of the microprocessor. The function of the NOP instruction is conventionally to generate a standby state during a period equal to one clock cycle.
Each instruction is processed during a period equal to a cycle, the so-called instruction cycle, which may be broken down into a cycle of searching for an instruction, a cycle of decoding the instruction, a cycle of executing the decoded instruction and a cycle of writing the result of the instruction.
Thus, if one wishes to generate a standby state during a period corresponding to N clock cycles of the microprocessor, the microprocessor is controlled according to N consecutive NOP instructions (see, FIG. 3).
Now, the implementation of these N instructions is on the one hand very expensive in terms of memory space (a memory space storing the program of the application) and monopolizes N instruction cycles to process the N NOP instructions. Moreover, with the microprocessor working for N instruction cycles, this also affects the energy consumption of the microprocessor. Specifically, the integrated circuits of the microprocessor are always active and are invoked to execute the instructions implementing the standby state, hence needless energy consumption. Indeed, the integrated circuits consume as much energy as during the execution of “useful” instructions of a program while they are carrying out no particular operation except the generation of a standby state. Moreover, it is known that the consumption of energy accelerates the deterioration of the integrated circuits on account of the increase in the resulting temperature in said circuits.
Thus, the processing time for the NOP instructions is long, expensive in terms of holding of memory space storing the program, so that such implementation is therefore hardly favorable for generating a standby state corresponding to a very significant number N of clock cycles.
Another procedure known from the prior (see, FIG. 4) proposes the implementation of a software loop comprising the aforesaid NOP instruction, and the number of iterations of which is dependent on the period of the standby state that one wishes to generate. This procedure is advantageous when N is large since it is less expensive in terms of memory space storing the program of the application.
A drawback of this procedure lies however in the implementation of the software loop which requires four instructions and, consequently, four instruction cycles of the microprocessor for the processing of one iteration of the loop (to be multiplied by the number of iterations of the loop).
Another drawback of this procedure is that the implementation also requires a counting register.
In another procedure known from the prior art (see, FIG. 5), it is also possible to program a counter external to the microprocessor. Several instructions are nevertheless necessary to program the period, then count and finally monitor the end of the count. Moreover, such a solution requires the addition of hard-wired logic components to produce a counter, this entailing extra manufacturing costs.
A last procedure known from the prior art proposes that an interrupt or an outside event be waited for on standby, in which case the period of the standby state is not determined since it depends on the moment at which the said interrupt or said outside event occurs.
However, this procedure makes it necessary to store in an external memory the address for resuming the execution of the program of the application. Moreover, it is rather inaccurate as regards the moment at which the standby state has to trigger and as regards the actual period of this standby state. This solution is therefore suitable for generating very long standby states in systems that do not require great accuracy. This procedure is not suitable however for certain computing or telecommunication systems whose applications are very sensitive to execution time (real-time applications, for example).
Finally, a drawback common to all the procedures known from the art is that when one wishes to modify the period of the standby state, the reprogramming is often tiresome and complex. This is generally true during the development phases of telecommunication or computing systems where the transfer rates have to be tailored via a standby state of a determined number of clock cycles. The development phase is yet more tedious.